logo

Tutorials – Nanoscale Technology – Transistor Modeling – IC Design

<<< back to tutorials <<<

Tutorial Title:

Joint ESSDERC/ESSCIRC Tutorial:
Nanoscale Technology – Transistor Modeling – IC Design


Chairs:

Wladek Grabiński (GMC, CH)
Daniel Tomaszewski (ITE, PL)


Abstract:

Our joint ESSDERC/ESSCIRC Tutorial aims to provide in-depth coverage of highly relevant R&D topics by world-class experts. We will discuss and present the frontiers of electron device modeling with emphasis on the complete UT SOI development chain, reviewing the nanoscale level technologies, devices TCAD numerical simulations, thru its simulation-aware compact/SPICE modeling up to selected topics of the transistor level IC design for advanced applications. This joint tutorial is designed for academic researchers, device process engineers who are interested in device modeling; academic/industrial ICs designers (to explore RF/Analog/Mixed-Signal) and those starting in these areas as well as device fabrication, electrical characterization, modeling and parameter extraction engineers. The content will be beneficial for
anyone who needs to learn what is really behind the IC fabrication and its simulation in using modern SPICE/Verilog-A device models.


Speakers:

TECHNOLOGY

open (Globalfoundiries, US) – UT SOI Processing and Device Fabrication
Eric Guichard (Silvaco, US) – UT SOI TCAD Numerical Process/Device Simulation

DEVICES

Mostafa Emam (Incize, B) – SOI RF Electrical Characterization
Thierry Poiroux (CEA-Leti, F) – UT SOI Compact Modeling

DESIGN

Christian Enz (EPFL, CH) – Transistor Level IC Design
Marcin Beresinski and Łukasz Kotynia (Cadence, PL) – Advanced SOI Design and Reliability/Ageing Simulations

 


<<< back to tutorials <<<