This keynote talk will highlight some of the emerging challenges and opportunities for next generation machine learning and hardware security technologies in the rapidly evolving IoT industry. With Moore’s law process technology scaling well into the nano-scale regime, future SoC platforms ranging from high performance cloud servers to ultra-low-power edge devices will demand advanced AI capabilities and stronger security features. New and emerging IoT markets for autonomous vehicles, drones, and wearables require even higher performance and security at much lower cost while reducing energy consumption. Some of the prominent barriers to designing high performance and energy-efficient multi-core microprocessors and SoCs in the sub-10nm technology nodes will be outlined. New paradigm shifts necessary for integrating special-purpose machine learning accelerators and hardware security processors into next-generation SoCs will be explored. Emerging trends in SoC circuit design for machine learning and deep neural networks, specialized accelerators for nearest-neighbor computing and reconfigurable multi-precision matrix multipliers, ultra-low-voltage logic and memory circuits, on-chip interconnect fabric circuits, ultra-lightweight encryption engines, physically unclonable functions, and fully-digital random number generator security building blocks are described. Future brain-inspired neuromorphic computing circuit design challenges and technologies will also be reviewed. Specific chip design examples and case studies supported by silicon measurements and trade-offs will be discussed.
Ram K. Krishnamurthy is a Senior Principal Engineer at Intel Labs, Hillsboro, Oregon. He directs the high performance and low voltage circuits research group. In this role, he leads research in high performance, energy efficient, and low voltage circuits for microprocessors and SoCs, and has made contributions to the circuit design of various generations of Intel products, including Intel® Itanium®, Pentium4®, Core®, Atom® and Xeon® line of microprocessors and SoCs. He has been at Intel Corporation since 1997. Krishnamurthy holds 125 issued patents with over 75 patents pending, and has published 200 papers and 3 book chapters on high performance energy efficient circuits. He serves as chair of the Semiconductor Research Corporation (SRC) technical advisory board for circuit design, and has been a guest editor of IEEE Journal of Solid-State Circuits, associate editor of IEEE transactions on VLSI systems, and on the technical program committees of ISSCC, CICC, and SOCC conferences. He served as Technical Program Chair/General Chair for the IEEE International Systems-on-Chip Conference and presently serves on the conference’s steering committee. Krishnamurthy serves as an adjunct faculty of the Electrical and Computer Engineering department at Oregon State University, where he taught advanced VLSI design. He is a board member of the industry advisory board for State University of New York. Krishnamurthy has received the IEEE International Solid State Circuits Conference distinguished technical paper award, IEEE European Solid State Circuits Conference best paper award, outstanding industry mentor award from SRC, Intel awards for most patents filed and most patents issued, Intel Labs Gordon Moore award, Carnegie Mellon University alumni recognition award, distinguished alumni award from State University of New York, MIT Technology Review’s TR35 innovator award, and recognized as a top ISSCC paper contributor. He has received two Intel Achievement Awards for pioneering the first 64b sparse-tree ALU technology and the first Advanced Encryption Standard accelerator on Intel products. He is a Fellow of the IEEE and distinguished lecturer of IEEE solid-state circuits society. Krishnamurthy received his BE in electrical engineering from National Institute of Technology in India (1993), MS in electrical and computer engineering from State University of New York (1994), and PhD in electrical and computer engineering from Carnegie Mellon University (1997).