Tutorials – Low Power/RF Circuits

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Tutorial Title:

Low-Power Analog/RF Circuits



Masoud Babaie (TU Delft, NL)

Teerachot Siriburanon (UCD, IE)

Venue: Medium Aula A



To support an exponential growth of Internet of Things (IoT) devices, there have been significant development of research in ultra-low-power radios and low-power sensors aiming to improve efficiency and reduce cost. This tutorial consists of six talks by leading experts in a variety of key aspects of low-power analog and radio-frequency (RF) circuits design for IoT and healthcare applications, in particular, recent advancements in low-power analog and radio-frequency (RF) circuits design. This tutorial will include wireless communication and power links for micro-implantables, design of switch-capacitor DC-DC converters, low-power SAR ADCs, ultra-low-power receivers, energy-efficient digital transmitter design for IoT and healthcare applications, and ultra-low-power DTC-Based fractional-N digital PLL techniques.



8:00 – 8:30 – Registration

8:30 – 8:45 – Introduction

8:45 – 10:00 – Amin Arbabian (Stanford University, US) – Wireless Communication and Power Links for Micro-Implantables

10:00 – 10:30 – Coffee break

10:30 – 11:45 – Ravi Karadi, Gerard Villar Pique (NXP Semiconductors, NL) – Design of Switched-Capacitor DC-DC Converters

11:45  – 13:00 – Pieter Harpe (TU Eindhoven, NL) – Low-Power SAR ADCs

13:00 – 14:00 – Lunch

14:15 – 15:30 – Antonio Liscidini (University of Toronto, CA) – Ultra-Low-Power Receivers

15:30 – 16:00 – Coffee break

16:00 – 17:15 – Yao-Hong Liu (Imec, NL) – Energy-efficient digital transmitter design for ingestible (swallowable) applications

17:15 – 18:30 – Kenichi Okada (Tokyo Institute of Technology, JP) – Ultra-Low-Power DTC-Based Fractional-N Digital PLL Techniques


Tutorial details

Speaker 1: Amin Arbabian, Stanford University, USA

Title: Wireless Communication and Power Links for Micro-Implantables



Highly miniaturized minimally invasive implants with wireless power and communication links have the potential to enable closed-loop treatments and precise diagnostics. As with wireless power transfer, robust wireless communication between implants and external transceivers presents challenges and tradeoffs with miniaturization and increasing depth. Both link efficiency and available bandwidth need to be considered for communication capacity. This talk will overview various electromagnetic and ultrasonic communication and power links for implantable devices. We’ll review circuits and systems for robust bi-directional links and explore opportunities in achieving high-rate ultrasonic data communication with deep tissue implants using available spatial degrees of freedom.



Amin Arbabian received his Ph.D. degree in EECS from UC Berkeley in 2011 and in 2012 joined Stanford University, as an Assistant Professor of Electrical Engineering. His current research interests include mm-wave and high-frequency circuits and systems, imaging technologies, Internet-of-Everything devices including wireless power delivery techniques, and medical implants. Prof. Arbabian currently serves on the steering committee of RFIC, the technical program committees of RFIC and ESSCIRC, and as associate editor of the IEEE Solid-State Circuits Letters (SSC-L) and the IEEE Journal of Electromagnetics, RF and Microwaves in Medicine and Biology (J-ERM). He is the recipient or co-recipient of the 2016 Stanford University Tau Beta Pi Award for Excellence in Undergraduate Teaching, 2015 NSF CAREER award, 2014 DARPA Young Faculty Award (YFA) including the Director’s Fellowship in 2016, 2013 Hellman faculty scholarship, and best paper awards from several conferences including ISSCC (2010), VLSI Circuits (2014), RFIC symposium (2008 and 2011, 2nd place), ICUWB (2013), PIERS (2015), MTT-S BioWireless symposium (2016), and BioCAS (2017).


Speaker 2: Ravi Karadi, Gerard Villar Pique, NXP Semiconductors, the Netherlands

Title: Design of Switched-Capacitor DC-DC Converters



Switched-capacitor DC-DC converters (SCPC) are an interesting option (in addition to the inductive converters) to realize power conversion needs, especially in the fully integrated applications with acceptable power efficiencies. They have the desirable features of using only capacitors and switches in the power stage (no inductors), and the power stage can be scaled easily to suit the load requirements. In this tutorial, we will cover the basic working principle, various SCPC topologies and the control techniques. We will start with the discussion of the basic workings of the SCPCs with some details of the various loss mechanisms.  Depending on the input and output voltage ranges to be accommodated at a desired efficiency, certain voltage conversion ratio(s) need(s) to be implemented. This requires knowledge of the SCPC topologies:  will present an overview of the various classical as well as recently discovered SCPC topologies covering both two-clock-phase topologies and multiple-clock-phase topologies. Then we will present and compare different control techniques of the SCPCs. We will present some implementation examples to illustrate the design issues and trade-offs in SCPCs.



Ravi Karadi received the M.Tech. degree in electrical engineering from the Indian Institute of Technology Delhi in New Delhi, India in 2006. He is currently a Principal Scientist in the field of power management in the with NXP Semiconductors in Eindhoven, the Netherlands. His main research interests include Switched-Mode Power Converters, (fully integrated) DC/DC converters, class-D audio amplifiers and analog circuit design.

Speaker 3: Pieter Harpe, TU Eindhoven, the Netherlands

Title: Low-Power SAR ADCs



With the development of Internet-of-Things, the demand for low-power radios and low-power sensors has been growing rapidly in the past decade. The Analog-to-Digital Converter (ADC) is one of the key building blocks in these systems to digitize information from the analog or RF domain to the digital domain. In this tutorial, an overview of low-power ADC architectures is given first, where the strong and weak points of each architecture are described, and limitations are investigated. Besides conventional architectures, several new developments like hybrid converters and noise-shaping SAR ADCs are introduced as well. After this overview, the talk will focus on low-power SAR ADCs, and the limits of power consumption, resolution, speed, and chip-area will be studied. Various concrete design examples from literature will be discussed in more detail to show some of the latest techniques that enable very low-power ADCs with state-of-the-art performance.



Pieter Harpe received the M.Sc. and Ph.D. degrees from the Eindhoven University of Technology, The Netherlands, in 2004 and 2010, respectively. In 2008, he started as researcher at Holst Centre/imec, The Netherlands. Since then, he has been working on ultra-low-power wireless transceivers, with a main focus on ADC research and design. In April 2011, he joined Eindhoven University of Technology where he is currently an Associate Professor on low-power mixed-signal circuits. Dr. Harpe is co-organizer of the yearly workshop on Advances in Analog Circuit Design (AACD) and analog subcommittee chair for the ESSCIRC conference. He also served as ISSCC ITPC member and IEEE SSCS Distinguished Lecturer and is recipient of the ISSCC 2015 Distinguished Technical Paper Award.

Speaker 4: Antonio Liscidini, University of Toronto, Canada

Title: Ultra-Low-Power Receivers



This talk will start with a brief introduction of the requirements of a wireless receiver and an overview of the most common architectures and techniques tailored for ultra-low power applications. In the second part of this presentation, the concept of current/device reuse will be discussed providing several examples as proof of the effectiveness of this strategy when applied to the area of low power transceivers. Current reuse technique will be analyzed in several way, form the design of the RF analog front-end up to the clock distribution and the analog base band.



Antonio Liscidini was born in Tirano, Italy, in 1977. He received the Laurea (summa cum laude) and Ph.D. degrees in electrical engineering from the University of Pavia, Pavia, Italy, in 2002 and 2006, respectively. He was a summer Intern with National Semiconductors, Santa Clara, CA, USA, in 2003, studying poly phase filters and CMOS low-noise amplifiers. From 2008 to 2012, he was an Assistant Professor with the University of Pavia and a Consultant with Marvell Semiconductors, Pavia, in the area of integrated circuit design. In 2012, he moved to the Edward S. Rogers Sr. Department of Electrical and Computer Engineering, University of Toronto, Toronto, ON, Canada, where he is currently an Associate professor. His research interests are focused on analog mixed signal interfaces with particular emphasis on the implementations of wireless transceivers and frequency synthesizers for cellular and ultra-low power applications. Dr. Liscidini was a recipient of the Best Student Paper Award at the IEEE 2005 Symposium on VLSI Circuits and a co-recipient of the Best Invited Paper Award at the 2011 IEEE Custom Integrated Circuit Conference. He has served as an Associate Editor for the IEEE Transactions on Circuits and Systems II: Express Briefs (2008-2011) (2017- 2018) and as a Guest Editor for the IEEE Journal of Solid-State Circuits (2013) (2016) and Guest Editor of the IEEE RFIC Virtual Journal (2018). Between 2016 and 2018, he has been a Distinguished Lecturer of the IEEE Solid-State Circuits Society. He has been member of the International Solid-State Circuit TPC (2012- 2017), member of the European Solid-State Circuit Conference TPC (2010- currently) and member of the Custom Integrated Circuit Conference TPC (2019-currently).

Speaker 5: Yao-Hong Liu, Imec-Netherlands, the Netherlands

Title: Energy-efficient digital transmitter design for ingestible (swallowable) applications



In this tutorial, several design challenges and state-of-the-art of  wireless transceiver for ingestible applications (e.g., capsule endoscopy) will be provided. In such applications, digital polar transmitter architecture is favoured because of the low-voltage operation, excellent energy efficiency, and capability of extensive self-calibration, etc. On the other hand, the constrain on power consumption, link budget and volume of ingestible wireless systems is at least an order more stringent than those for wearable or IoT applications. Several new design approaches and low-power implementation of the digital polar transmitters, including digital PA and PLL, will be discussed. A design example of a sub-nJ/b OFDM digital polar transmitter for ingestible will also be included.



Yao-Hong Liu received his Ph.D. degree from National Taiwan University,Taiwan, in 2009.

He was with Terax, Via Telecom (now Intel), and Mobile Devices, Taiwan, from 2002 to 2010, working on Bluetooth, WiFi and cellular wireless SoC products. Since 2010, he joined imec, the Netherlands. His current position is Principal Membership of Technical Staff, and he is leading the development of the ultra-low power (ULP) RFIC design. His research focuses are energy-efficient wireless transceivers and radar for IoT and healthcare applications.

He currently serves as a technical program committee of IEEE ISSCC and RFIC symposium.

Speaker 6: Kenichi Okada, Tokyo Institute of Technology, Japan

Title: Ultra-Low-Power DTC-Based Fractional-N Digital PLL Techniques



In this presentation, some design techniques for fractional-N digital PLL will be introduced to improve both jitter and power consumption for low-power wireless applications. A highly-linear and low-power DTC and TDC will be presented as well as system-level optimization. An isolated constant-slope DTC realizes 10bit 0.1mW operation with 26MHz reference clock, and sub-ps INL is achieved. The DTC-based AD-PLL achieves FoM of -246dB with 0.98mW power consumption and -56dBc worst-case fractional spur. For further power saving, duty-cycled FLL, sub-sampling/sampling switching, charge-recycling DTC, and transformer-based DCO for impedance peaking will be also explained, which achieves 0.265mw power consumption with FoM of -237dB at 2.4GHz. Finally, a DPLL-based ADC and a BLE transceiver using DPLL will be introduced.



Kenichi Okada received the B.E., M.E., and Ph.D. degrees from Kyoto University, Kyoto, Japan, in 1998, 2000, and 2003, respectively. He joined Tokyo Institute of Technology in 2003, and he is now Associate Professor. He has authored and co-authored more than 400 journal and conference papers. His current research interests include millimeter-wave wireless transceiver, digital PLL, and ultra-low-power RF circuits. He has worked as a TPC member of ISSCC, VLSI Circuits, and ESSCIRC, and Guest editors and Associate Editor of JSSC.

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