Basics of Jitter and Phase Noise
Ali Sheikholeslami (University of Toronto, CA)
Jitter and Phase Noise characterize the timing precision of clock and data signals in a variety of applications such as data converters, wireline, and wireless systems. The first talk in this tutorial provides the basic definitions of jitter and phase noise, their properties, and their relationship to each other. This talk will form the foundation for the subsequent three talks. The second talk will discuss how jitter is converted to noise in data converters, thereby affecting the signal-to-noise ratio, and the effective number of bits in an ADC. This talk will also show how, in wireline communications, jitter reduces the timing margin available for clock and data recovery (CDR) circuits and poses significant challenges to signal integrity as the data rates march towards 100Gb/s/lane and beyond. In the third talk, phase noise in oscillators will be discussed. After a theoretical analysis of the phase noise generation in oscillators, several topologies will be compared with some emphasis on harmonic CMOS oscillators. In particular, this talk will show the evolution through the different class of operation from class B to class F by highlighting the pros and cons of each topology. The final talk in this tutorial will discuss the impact of phase noise in wireless applications. After an overview of the mechanisms that set the most challenging phase noise requirement in wireless transceivers, such as reciprocal mixing and modulation of the local oscillator, the structure of a typical frequency synthesizer will be analyzed by highlighting the most critical sources of phase noise. This talk ends with an overview of the metrics which relate phase noise and power dissipation in phase locked loop.
Ali Sheikholeslami (University of Toronto, CA) – Fundamental Concepts in Jitter and Phase Noise
Nicola Da Dalt (AMD, US) – Jitter in Wireline and Data Converter Applications
Piero Andreani (Lund University, SE) – Phase Noise in Oscillators
Antonio Liscidini (University of Toronto, CA) – Phase Noise in Wireless Applications
Speaker 1: Ali Sheikholeslami, University of Toronto, CA
Title: Fundamental Concepts in Jitter and Phase Noise
Jitter and Phase Noise characterize the timing precision of clock and data signals in a variety of applications such as data converters, wireline, and wireless systems. This talk provides basic definitions of various types of jitter and phase noise, how they manifest themselves in different applications, and how they all relate to each other. The aim of this talk is to provide an intuitive understanding of jitter and phase noise and to serve as a foundation for the next three talks in this tutorial.
Ali Sheikholeslami received the B.Sc. degree from Shiraz University, Iran, in 1990 and the M.A.Sc. and Ph.D. degrees from the University of Toronto, Canada, in 1994 and 1999, respectively, all in electrical engineering. In 1999, he joined the Department of Electrical and Computer Engineering at the University of Toronto where he is currently Professor. He was on research sabbatical with Fujitsu Labs in 2005-2006, and with Analog Devices in 2012-2013. His research interests are in analog and digital integrated circuits, high-speed signaling, VLSI memory design, and CMOS annealing. He has coauthored over 70 journal and conference papers, 10 patents, and a graduate-level textbook entitled “Understanding Jitter and Phase Noise – A Circuits and Systems Perspective”, Cambridge University Press. He was a co-author of the CICC2017 Outstanding Student Paper Award. Dr. Sheikholeslami served on the Memory, Technology Directions, and Wireline Subcommittees of the ISSCC in 2001-2004, 2002-2005, and 2007-2013, respectively. He currently serves as the Education Chair for both ISSCC and the Solid-State Circuits Society (SSCS). He is a Distinguished Lecturer (DL) of the Society and oversees its DL and webinar programs. He is an Associate Editor for the Solid-State Circuits Magazine, in which he has a regular column entitled “Circuit Intuitions”. He was an Associate Editor for the IEEE TCAS-I for 2010-2012, and the program chair for the 2004 IEEE ISMVL. Dr. Sheikholeslami has received numerous teaching awards including the 2005-2006 Early Career Teaching Award and the 2010 Faculty Teaching Award, both from the Faculty of Applied Science and Engineering at the University of Toronto. He is a registered professional engineer in Ontario, Canada.
Speaker 2: Nicola Da Dalt, AMD, US
Title: Jitter in Wireline and Data Converter Applications
This talk will discuss the fundamental, first-order aspects of jitter in wireline and data converters applications. The wireline part will focus mainly on the operation of a classical Clock and Data Recovery unit and will analyze the concepts of Jitter Generation, Jitter Transfer and Jitter Tolerance. The data converter part will first describe the effect of jitter on DACs and how to calculate the resulting SNR. Subsequently, the effect of jitter on basic operation of Nyquist ADCs, Sigma Delta ADCs, and the resulting performance degradation will be covered.
Nicola Da Dalt received the M.S. degree from the University of Padova, Italy, in 1994 and the Ph.D. degree from RWTH Aachen, Germany, in 2007, both in electrical engineering, with distinction. From 1996 to 1998 he was with CSELT, Turin, Italy, as a concept engineer for architectures and synchronization of data transmission networks. From 1998 to 2015 he was with Infineon Technologies, Villach, Austria, as Lead Principal engineer for analog mixed-signal design, and manager of the Clock and Interface Systems group. From 2015 to 2018 he was with the Programmable Solution Group of Intel Corporation, San Jose, California, as Analog Engineering Manager for the development of high-speed serial interfaces for FPGA applications. Since 2018 he has been with AMD, Santa Clara, California as Silicon Design Engineering Director, focusing on high-speed wireline transceivers. Dr. Da Dalt served on the Wireline Subcommittee of the ISSCC from 2011 to 2015. He is the recipient of the 2010 IEEE Transactions on Circuits and Systems Guillemin-Cauer Best Paper Award for his pioneering work on digital bang-bang PLLs, and the recipient of the 2017 ISSCC Outstanding Forum Speaker Award. He is co-author of the book “Understanding Jitter and Phase Noise – A Circuits and Systems Perspective”, Cambridge University Press. He has co-authored over 30 journal and conference papers and 12 granted patents.
Speaker 3: Pietro Andreani, Lund University, SE
Title: Phase Noise in Oscillators
As one of the truly fundamental analog functions in any wireless/wireline application, the voltage-controlled oscillator keeps attracting a great deal of well-deserved attention. In this presentation, we will investigate the mechanisms of phase noise generation in harmonic oscillators, including some recently published general results, after which we will analyze both classical and emergent oscillator architectures, describing pros and cons for each. Various techniques to achieve a very wide oscillator tuning range, and their impact on phase noise, will be illustrated as well.
Pietro Andreani received the M.S.E.E. degree from the University of Pisa, Italy, in 1988, and the Ph.D. degree from Lund University, Sweden, in 1999. Between 2001 and 2007 he was chair professor at the Center for Physical Electronics, Technical University of Denmark. From 2005 to 2014 he had a 20% position as analog/RF designer at Ericsson AB in Lund, Sweden. Since 2007, he has been associate professor at the dept. of Electrical and Information Technology (EIT), Lund University, working in analog/mixed-mode/RF IC design. He was also the head of the VINNOVA Center for System Design on Silicon, hosted by EIT (2014-2016). He has been a TPC member of ISSCC (2007-2012), is a TPC member of ESSCIRC (chair of the Frequency Generation subcommittee since 2012, TPC chair in 2014) and RFIC, and an Associate Editor of JSSC. He was an IEEE SSCS Distinguished Lecturer in 2017-2018. He has authored numerous papers on oscillators and phase noise.
Speaker 4: Antonio Liscidini, University of Toronto
Title: Phase Noise in Wireless Applications
This talk will discuss the impact of phase noise in wireless applications. After an overview of the mechanisms that set the most challenging phase noise requirement in wireless transceivers, such as reciprocal mixing and modulation of the local oscillator, the structure of a typical frequency synthesizer will be analyzed by highlighting the most critical sources of phase noise. The talk will end with an overview of the metrics which relate phase noise and power dissipation in phase locked loop.
Antonio Liscidini was born in Tirano, Italy, in 1977. He received the Laurea (summa cum laude) and Ph.D. degrees in electrical engineering from the University of Pavia, Pavia, Italy, in 2002 and 2006, respectively. He was a summer Intern with National Semiconductors, Santa Clara, CA, USA, in 2003, studying poly phase filters and CMOS low-noise amplifiers. From 2008 to 2012, he was an Assistant Professor with the University of Pavia and a Consultant with Marvell Semiconductors, Pavia, in the area of integrated circuit design. In 2012, he moved to the Edward S. Rogers Sr. Department of Electrical and Computer Engineering, University of Toronto, Toronto, ON, Canada, where he is currently an Associate professor. His research interests are focused on analog mixed signal interfaces with particular emphasis on the implementations of wireless transceivers and frequency synthesizers for cellular and ultra-low power applications. Dr. Liscidini was a recipient of the Best Student Paper Award at the IEEE 2005 Symposium on VLSI Circuits and a co-recipient of the Best Invited Paper Award at the 2011 IEEE Custom Integrated Circuit Conference. He has served as an Associate Editor for the IEEE Transactions on Circuits and Systems II: Express Briefs (2008-2011) (2017- 2018) and as a Guest Editor for the IEEE Journal of Solid-State Circuits (2013) (2016) and Guest Editor of the IEEE RFIC Virtual Journal (2018). Between 2016 and 2018, he has been a Distinguished Lecturer of the IEEE Solid-State Circuits Society. He has been member of the International Solid-State Circuit TPC (2012- 2017), member of the European Solid-State Circuit Conference TPC (2010- currently) and member of the Custom Integrated Circuit Conference TPC (2019-currently).