Circuits and Systems Enabling Quantum Technologies
Edoardo Charbon (EPFL, CH)
Quantum technologies hold the promise to fundamentally change computing and other fields as we know them today. Most quantum technologies are based on quantum bits (qubits), which require to be constantly controlled, so as to ensure proper operation at deep-cryogenic temperatures. Electronic instruments operating at room temperature usually perform this control task, which also includes readout and evaluation. However, with the growth of qubit numbers, the complexity of these instruments is bound to increase exponentially, thus hindering the achievement of scalable quantum systems. Recently, a growing number of researchers has suggested moving the control electronics to cryogenic temperatures, to operate close to the qubits. In this tutorial, we capture this trend with nine speakers active in this field. We will discuss the latest developments of the field with focus on cryogenic ICs leveraging over 60 years of technological advances in integrated electronics to ultimately achieve fully cryogenic systems for truly scalable quantum computers.
Jonathan Baugh (Univ. of Waterloo, CA) – Network architecture for a surface code quantum computer in silicon
Tristan Meunier, Silvano DeFranceschi (LETI, FR) – Towards scalable silicon quantum computing
Christian Enz (EPFL, CH) – MOSFET Modeling down to Cryogenic Temperatures
Philippe Galy (STMicroelectronics, FR) – FD-SOI CMOS technology towards silicon quantum applications with its cryogenic condition
M. Fernando Gonzalez-Zalba (Cambridge University, GB) – A dynamic random access architecture based on FDSOI technology for radio-frequency readout of quantum devices
Sorin Voinigescu (Univ. of Toronto, CA) – Towards monolithic quantum computing processors in production FD-SOI CMOS technology
Fabio Sebastiano (TU Delft, NL) – Cryogenic CMOS interfaces for large-scale quantum computers: from system and device models to circuits
Joseph Bardin (Univ. of Massachusetts at Amherst, US) – CMOS Integrated Circuits for Control of Transmon Qubits
Masoud Babaie (TU Delft, NL) – Benefits and Challenges of Designing Cryogenic CMOS RF Circuits for Quantum Computers
Speaker 1: Jonathan Baugh, University of Waterloo, Waterloo, Canada
Realizing a large-scale, universal quantum computer would enable major technological advances, yet presents a significant challenge. The standard circuit model for quantum computation requires a staggering error correction overhead to achieve fault tolerance. Topological stabilizer codes acting on two-dimensional qubit arrays, i.e. surface codes, can tolerate relatively high error thresholds and are very promising for scalability. I will present a brief introduction to quantum error correction, targeted to a non-quantum audience, to convey how fault tolerance is achieved in quantum computation. I will then describe our recent proposal for a network-of-nodes architecture that should allow practical scaling for a CMOS electron spin qubit processor.
Jonathan Baugh is working toward the physical realization of quantum information processors in the solid-state, using the property of spin to encode and manipulate quantum information. Past work has focused on solid-state electron and nuclear magnetic resonance devices, and more recently on nanoelectronics devices including quantum wires and dots. Prior to joining the Institute for Quantum Computing at the University of Waterloo as a faculty member in 2007, he spent several years as a postdoctoral scholar and one year as a visiting researcher at the University of Tokyo. He received a PhD in Physics in 2001 from the University of North Carolina at Chapel Hill.
Speaker 2: Tristan Meunier, CNRS Institut Néel, University Grenoble Alpes, France
General considerations and recent achievements important to go to large-scale quantum computing in silicon will be discussed. The discussion will focused first on building deterministic and repeatable high quality, high fidelity qubit gates; second to demonstrate them within 2D arrays; and third to draw a projection on what a quantum computer based on Si would look like based on the learning of the two previous conditions. From a technological perspective, one main advantage of switching from lab to industry-like technology will be to provide access to advanced VLSI technology like 3D-integration to enable scaling of quantum systems in Si.
Dr Tristan Meunier (CNRS Institut Néel, University Grenoble Alpes, France) is a CNRS researcher working at Institut Néel. His research interests are mainly in the field of coherent control of individual quantum objects, both in atomic physics and solid-state systems. Since 2005, he participates to the world-wide effort on the coherent control of individual electron spins in semiconductors. He received the Starting and Synergy Grants of the European Research Council (ERC) on the coherent control of individual electron spins in semiconductor nanostructures respectively in 2012 and 2018 (synergy together with Maud Vinet and Silvano DeFrancheschi).
Speaker 3: Christian Enz, EPFL, Lausanne, Switzerland
There is currently a large effort to try to miniaturize quantum computers taking advantage of solid-state technologies enabling a potentially large number of qubits. CMOS is the preferred technology for building the qubit array and mixing it with the control and readout electronics taking advantage of the cryogenic temperature to operate the electronics at lower power and/or faster. The design and optimization of these CMOS analog and digital circuits need to have a compact transistor model that is valid down to cryogenic temperatures. Unfortunately, the MOSFET compact models available today do not scale properly with temperature down to such low temperature. This presentation will address this limitation. It starts with an assessment of the analog performance at cryogenic temperatures using the simplified EKV MOSFET model. The main effects occurring at cryogenic temperature are described and a physics-based MOSFET model that scales down to ultra-low temperatures is presented.
Christian Enz earned is PhD from EPFL in 1989. He is currently Professor at EPFL, Director of the Institute of Microengineering and head of the IC Lab. Until April 2013 he was VP at the Swiss Center for Electronics and Microtechnology (CSEM), where he was heading the Integrated and Wireless Systems Division. Prior to joining CSEM, he was Principal Senior Engineer at Conexant (formerly Rockwell Semiconductor Systems), Newport Beach, CA, where he was responsible for the modeling and characterization of MOS transistors for RF applications. His technical interests and expertise are in the field of ultralow-power analog and RF IC design and semiconductor device modeling. Together with E. Vittoz and F. Krummenacher he is the developer of the EKV MOS transistor model and the author of the book “Charge-Based MOS Transistor Modeling – The EKV Model for Low-Power and RF IC Design” (Wiley, 2006). He is the author and co-author of more than 260 scientific papers and has contributed to numerous conference presentations and advanced engineering courses. He is an IEEE Fellow and an individual member of the Swiss Academy of Engineering Sciences (SATW).
Speaker 4: Philippe Galy, STMicroelectronics, Crolles, France
CQFD: It is well know that FD-SOI advanced CMOS technology is a good candidate for SOC integration and for Low power applications. In this talk, we will give an overview of the 28nm FD-SOI technology with its key parameters and results. Afterward, we will discuss quantum application and cryogenic temperature condition. Preliminary silicon results and innovative solutions in 28nm STMicroelectronics technology are introduced according to these challenges.
Philippe Galy was born in 1965; he received the Ph.D. from University of Bordeaux and H.D.R from LAAS CNRS University of Toulouse. He is a fellow and technical director at STmicrolectronics Research and Development France. He has proposed a full CDM protection and several new ESD compact devices for mature & advanced CMOS technologies. He supports several teams for research focused on new innovative solutions: Memory + silicon Qubit and cryo-design, Neuromorphic, 3D ultimate integration. He has authored or coauthored several publications (+100), books (3), and patents (+100). He serves in the TPC of and is a reviewer for many symposiums and journals. He is also involved in National (3) and European projects (3). Also he joins the QuEng CDP team from Grenoble.
Speaker 5: M. Fernando Gonzalez-Zalba, Cambridge University, U.K.
Quantum computing is maturing at a relentless pace, yet individual quantum bits are wired one by one. As quantum processors become more complex, they will require efficient interfaces to deliver signals for control and readout while keeping the number of inputs manageable. Digital electronics could offer solutions to the scaling challenge by leveraging established industrial infrastructure to interface silicon-based quantum devices with conventional CMOS circuits. Here, we combine both technologies at millikelvin temperatures and demonstrate the building blocks of a dynamic random access architecture for efficient readout of complex quantum circuits. Our results demonstrate a path to reducing the number of input lines per qubit and enable addressing of large arrays of devices.
Fernando is Senior Scientist and Head of Quantum Information at the Hitachi Cambridge Laboratory, the R&D centre of Hitachi Europe Ltd. on fundamental device physics. His research is focused on new computing paradigms and more recently on the development of a silicon-based quantum computer. He received the PhD from the University of Cambridge with a thesis on Single-atom Electronics in 2013, he received the R&D Technology Award from Hitachi’s Centre for Social Innovation for the development of the aforementioned technology in 2016 and he was awarded the Young Scientist Award by the Spanish Royal Society of Physics in 2017. Fernando’s research is funded by the European Commission’s H2020 program, EPSRC and the Winton Programme for the Physics of Sustainability. He has published more than 30 peer reviewed articles, has 3 granted patents and often participates in outreach scientific events for all ages.
Speaker 6: Sorin Voinigescu, University of Toronto, Toronto, Canada.
This presentation will discuss the feasibility of high-temperature (2-4 K) Si and SiGe electron/hole-spin qubits and qubit integrated circuits (ICs) in commercial 22nm FD-SOI CMOS technology, and demonstrate the advantage of the SiGe channel hole-spin qubit over its silicon-only electron-spin counterpart. It is also shown that, at 2 K, MOSFETs and cascodes can be operated as quantum dots in the subthreshold region, while behaving as classical MOSFETs and cascodes in the saturation region, suitable for qubits and mm-wave mixed-signal processing circuits, respectively.
Sorin P. Voinigescu holds the Stanley Ho Chair in Microelectronics and is the Director of the VLSI Research Group in the Electrical and Computer Engineering Department at the University of Toronto. He is an IEEE Fellow and a world-renowned expert on millimeter-wave and 100+Gb/s integrated circuits and atomic-scale semiconductor device technologies.
Speaker 7: Fabio Sebastiano, Delft University of Technology, Delft, Netherlands.
Quantum computers operate by processing information stored in quantum bits (qubits), which must typically operate at cryogenic temperature. A practical quantum computer will comprise thousands of qubits, thus requiring an electronic interface also operating at cryogenic temperature to ensure integration and scalability of the whole system. Focusing on the use of standard CMOS technology, we will explore the challenges in building such interface, comprising modeling of the quantum/classical interface, devices modeling for cryogenic CMOS and the design of high-performance cryogenic CMOS circuits. By demonstrating the cryogenic operation of complex CMOS analog and digital systems, we will show that cryogenic CMOS is a viable technology to enable large-scale quantum computing.
Fabio Sebastiano holds degrees in Electrical Engineering from University of Pisa, Italy (BSc, 2003; MSc, 2005) from Sant’Anna school of Advanced Studies, Pisa, Italy (MSc, 2006) and from Delft University of Technology, The Netherlands (PhD, 2011). From 2006 to 2013, he was with NXP Semiconductors Research in Eindhoven, The Netherlands. In 2013, he joined Delft University of Technology, where he is currently an Assistant Professor. He has authored or co-authored one book, ten patents, and over 60 technical publications. His main research interests are cryogenic electronics for quantum applications, sensor read-outs and frequency references. Dr. Sebastiano was the co-recipient of the best student paper award at ISCAS in 2008, the best paper award at IWASI in 2017 and the best IP award at DATE in 2018. He is a senior member of IEEE, a TPC member for RFIC and a Distinguished Lecturer of the IEEE Solid-State Circuit Society.
Speaker 8: Joseph Bardin, University of Massachusetts, Amherst, U.S.A.
Future quantum computing systems will require cryogenic integrated circuits to control and measure millions of qubits. In this talk, we will first describe the unique challenges inherent to the control of superconducting qubits. Next, we will present the design and measurement of a prototype cryogenic CMOS integrated circuit that has been optimized for the control of transmon qubits. The circuit has been integrated into a quantum measurement setup and its performance has been validated through multiple quantum control experiments. The talk will conclude with a discussion of challenges that must be overcome to enable scalable quantum computing.
Joseph Bardin received the PhD in electrical engineering from California Institute of Technology in 2009. In 2010, he joined the department of Electrical and Computer Engineering at the University of Massachusetts Amherst, where he is currently an Associate Professor. His research group pursues a wide range of topics related to integrated circuits for low-temperature applications, including radio astronomy, quantum optics, and quantum computing. Since the summer of 2017, he has also been with the Google Quantum AI group, where he has investigated the use cryogenic integrated circuits for quantum computing. He has been the recipient of several awards including the DARPA YFA Award, the NSF CAREER Award, the ONR YIP Award, the UMass College of Engineering Outstanding Junior Faculty Award, and the UMass Award for Outstanding Accomplishments in Research and Creative Acitivites.
Speaker 9: Masoud Babaie, Delft University of Technology, Delft, Netherlands.
Accurate and low-noise generation and amplification of microwave signals are required for the manipulation and readout of quantum bits (qubits). A fault-tolerant quantum computer operates at deep cryogenic temperatures (i.e. <100 mK) and requires thousands of qubits for running practical quantum algorithms. CMOS radio-frequency (RF) integrated circuits operating at cryogenic temperatures down to 4K (Cryo-CMOS) can offer a higher level of system integration and scalability for future quantum computers. In this presentation, I extensively discuss the role, benefits, and constraints of cryogenic CMOS RF circuits for control and readout of quantum bits. The main characteristics of the CMOS transistors and their impacts on RF circuit designs are described. Furthermore, opportunities and challenges of low-noise RF signal generation and amplification are investigated.
Masoud Babaie received the Ph.D. degree (cum laude) in electrical engineering from the Delft University of Technology in 2016. In 2006, he joined the Kavoshcom Research and Development Group, Tehran, where he was involved in designing wireless communication systems. From 2009 to 2011, he was a CTO of that company. From 2014 to 2015, he was a Visiting Scholar Researcher with the Berkeley Wireless Research Center, Berkeley, CA, USA. In 2016, he joined Delft as an Assistant Professor. His current research interests include RF/millimeter- wave integrated circuits and systems for wireless communications, and cryogenic electronics for quantum computation. Dr. Babaie has been a Committee Member of Student Research Preview (SRP) of the IEEE International Solid-State Circuits Conference (ISSCC), since 2017. He was a recipient of the 2015–2016 IEEE Solid-State Circuits Society Pre-Doctoral Achievement Award.