5G Radios: Concepts, Systems, and Silicon
Gernot Hubert (Silicon Austria Labs, AT),
Francois Rivet (IMS Bordeaux, FR)
Venue: Main Auditorium B
The future of mobile communication specified in 5G includes sub-6 GHz frequency bands, mm-Wave frequencies (28 GHz, 39 GHz) for very high throughput in enhanced Mobile Broadband, Ultra Reliable Low Latency Communications and Massive Machine Type Communication. This diversity including their specific challenges demands from RFIC designers to discover innovative architectures and smart techniques to enable novel products. This workshop will provide the community in-depth understanding of new and underlying concepts and systems in 5G, including the advantages and challenges of Massive MIMO and beam-forming, as well as RFIC design examples such as 5G mm-Wave circuits for transceivers and key building blocks.
The motivation of this workshop is to capture the lead-edge of IC design, what is the demand of the industry in the context of innovation in line with novel process technologies, as well, what are circuit and architectural concepts that are demanded. We focus especially on RFIC circuits design and technologies competing for today’s and tomorrow’s applications in 5G.
8:00 – 8:30 – Registration
8:30 – 9:00 – Introduction
9:00 – 10:00 – Fredrik Tillman (Ericsson, SE) – Going from a 5G Vision to Real Implementation
10:00 – 10:30 – Coffee break
10:30 – 11:30 – Marc Tiebout (Infineon, AT) – RFIC Design in BiCMOS for 5G mmWave Phased Arrays
11:30 – 12:30 – Ewout Martens (Imec, BE) – Advanced Techniques for ADCs for 5G Massive-MIMO
12:30 – 13:45 – Lunch
13:45 – 14:45 – Baudouin Martineau (CEA-LETI, FR) – Opportunity of CMOS FD-SOI for 5G
14:45 – 15:45 – Mirjana Videnovic-Misic (Silicon Austria Labs, AT) – Body Biasing in 28nm UTBB FD-SOI CMOS Technology – a Device Approach to enable 5G RFICs
15:45 – 16:15 – Coffee break
16:15 – 17:15 – Andreia Cathelin (STMicroelectronics, FR) – FD-SOI integration solutions for 5G Applications
17:15 – 18:00 – Gernot Hubert (Silicon Austria Labs, AT) – Very high Data-rate RF Systems for beyond 5G
Speaker 1: Fredrik Tillman (Ericsson, SE)
Title: Going from a 5G Vision to Real Implementation
Abstract:
Stretching beyond traditional mobile access, 5G is on a quest to transform connectivity as we know it today. With the ambition to provide data sharing anywhere at any time, for anyone and anything, the implementation challenges are demanding. This will also change the network deployment strategy and associated hardware realization in a profound way. On top, the spectrum availability has never been more diverse, which will further challenge traditional architectural approaches. This workshop presentation will highlight different 5G scenarios and their implications on the transceiver hardware. Transceiver block level requirements will be discussed, as well as tradeoffs in terms of building practice, antenna integration, and cost.
Bio:
Fredrik Tillman received his Msc and PhD in Circuit Design from Lund University in 2000 and 2005 respectively. From 2006 through 2007 he worked on CMOS RF ASIC design at Ericsson Mobile Platforms in Lund (Sweden) and Raleigh (USA). Since 2008 Dr. Tillman has been a technical manager at Ericsson Research with focus on CMOS circuit design, and acted as the Ericsson responsible for several European collaboration projects. In 2015 Dr. Tillman worked on the Ericsson radio DOT system in Ottawa (Canada) and is currently heading the Integrated Radio Systems department at Ericsson Research.
Speaker 2: Marc Tiebout (Infineon, AT)
Title: RFIC Design in BiCMOS for 5G mmWave Phased Arrays
Abstract:
The infrastructure deployment of mm-Wave 5G telecommunications requires cost-effective, worldwide usable, easy to calibrate and long-term reliable RFICs. This talk will start with worldwide standardization requirements for infrastructure, next go into optimal technology choice, adequate system and RFIC partitioning, before introducing a BiCMOS RFIC chip set supporting wordwide 5G mmWave deployment. Last but not least the topic of integrated built in test equipment supporting production testing and phased array calibration will be presented.
Bio:
Marc Tiebout (S’90-M’93) was born in Asse, Belgium, in 1969. He received the M.Sc. degree in electrical and mechanical engineering in 1992 from the Katholieke Universiteit Leuven, Belgium, and the Ph.D. degree in electrical engineering from the Technical University of Berlin, Germany, in 2004. In 1993, he joined Siemens AG, Corporate Research and Development, Microelectronics in Munich, Germany, designing analog integrated circuits in CMOS and BiCMOS technologies. From 1999 to 2005, he was with Infineon Technologies AG, Munich, Germany, where he worked on RFCMOS circuits and transceivers for cellular wireless communication products and conducted highest frequency RFCMOS research for 17 and 24 GHz applications. Since 2006, he is with Infineon Technologies, Villach, Austria where his work includes Wimedia-UWB CMOS SoC development and mmWave phased-array applications for radar, security and communications up to 80GHz. He has authored and co-authored more than 100 IEEE publications and more than 45 patents.
Speaker 3: Ewout Martens (Imec, BE)
Title: Advanced Techniques for ADCs for 5G Massive-MIMO
Abstract:
Advanced Techniques for ADCs for 5G Receivers Abstract: In 5G systems, ADCs play a key role to increase the capacity and flexibility of the network. Depending on the system architecture, different scenarios result in different requirements for the ADCs. In handheld devices, focus is on low power design solutions and high bandwidths with moderate accuracy. In baseband stations, recent advances in technology and design techniques enable low-power Giga-sampled ADCs supporting direct-RF architectures. For massive MIMO systems, low-power, low-area solutions are needed to realize digital-intensive architectures. To accommodate for different use cases, flexible ADCs with e.g. a variable resolution are preferred. Design cases of ADCs suitable for high-performant 5G systems will be discussed.
Bio:
Ewout Martens (M’08) was born in Genk, Belgium,in 1978. He received the M.Sc. degree in 2001 and Ph.D. degree (summa cum laude) in 2007 from the Katholieke Universiteit Leuven, Belgium. From 2001 to 2007, he was a Research Assistant with ESAT-MICAS Laboratories of the Katholieke Universiteit Leuven. His Ph.D. research was on model-ing of Delta-Sigma modulators and RF front-ends.He joined imec (SSET), Belgium, in 2010 as a Design Engineer for WLAN transceivers. His interests and work are related to the development of innovative
architectures for RF receiver front-ends, transceiver building blocks like PLL, filters and LNA, and ADCs for various applications including image sensors and wireless receivers.
Speaker 4: Baudouin Martineau (CEA-LETI, FR)
Title: Opportunity of CMOS FD-SOI for 5G
Abstract:
CMOS circuits operating from analog to RF have proven their capability to satisfy the market demand in terms of cost and high volume capability. However, the upcoming RF to millimeter wave products from Iot to 5G need improvements of performances and efficiency. This talk attents to demonstrate that FD-SOI technologies are not only suitable for low power but also for high power RF circuit if proper design taking benefits of the technology is adopted.
Bio:
Baudouin Martineau received the Ph.D. degree in microwave and microtechnology in 2008. His Ph.D. thesis focused on the 65nm CMOS SOI potentialities for millimeter wave wireless applications. In 2008, he joined the Technology R&D department of STMicroelectronics and now he is with CEA-LETI Research Institute as senior research engineer in Analog-RF & mmW design activity.
Speaker 5: Mirjana Videnovic-Misic (Silicon Austria Labs, AT)
Title: Body Biasing in 28nm UTBB FD-SOI CMOS Technology – a Device Approach to enable 5G RFICs
Abstract:
As wireless networks are transitioning to 5G, there is a high demand for innovative wideband transceivers that will support growing number of bands in an area and cost efficient manner. Stringent system level requirements, new application scenarios together with continuing downscaling and voltage supply decrease impose novel design methodologies and use of innovative semiconductor technologies like 28nm UTBB FD SOI CMOS. In this presentation, body biasing technique advantage given to a mixer-first receiver design will be explained from the device
perspective. Area and circuit complexity reduction will be achieved for class A and class AB amplifiers while keeping a tight control over important figures of merit in all process corners.
Bio:
Dr. Mirjana Videnović-Mišić received her PhD degree from the University of Novi Sad, Serbia, in 2009. From 2010 to 2016 she was an Assistant Professor at the Department of Electronics, Faculty of Technical Sciences, University of Novi Sad, Serbia. Dr. Videnović-Mišić was Fulbright Visiting Scholar at UC Berkeley from 09/2014-06/2015 and Marie Sklodowska Currie Fellow from 07/2015-06/2018. Her research interests include noise modelling of submicron components, design and optimization of analog and radio-frequency integrated circuits for the next generation mobile devices. Dr. Videnović-Mišić joined Silicon Austria Labs in 2018.
Speaker 6: Andreia Cathelin (STMicroelectronics, FR)
Title: FD-SOI integration solutions for 5G Applications
Abstract:
This tutorial presentation will first present a very short overview of the major analog and RF/mmW technology features of the 28nm FDSOI technology. Then we will focus on the benefits in the view of 5G applications. Design examples such as a 30GHz 5G Power Amplifier, as well as an IoT Ultra Low Power SoC for WSN are given. A special focus will be done on the advantages of the unique features of body biasing in FD-SOI and specific design techniques offering state of the art performance.
Bio:
Andreia Cathelin (M’04, SM’11) started electrical engineering at the Polytechnic Institute of Bucarest, Romania and graduated from ISEN Lille, France in 1994. In 1998 and 2013 respectively, she received PhD and “habilitation à diriger des recherches” (French highest academic degree) from the Université de Lille 1, France. Since 1998, she has been with STMicroelectronics, Crolles, France, now Technology R&D Fellow. Her focus areas are in the design of advanced RF/mmW/THz and ultra-low-power circuits and systems. Andreia has had numerous responsibilities inside IEEE since more than 15 years: at ISSCC, VLSI Symposium and ESSCIRC for TPC and Executive/Steering Committees respectively, and has been SSCS elected Adcom member 2015 to 2017. Andreia is a co-recipient of the ISSCC 2012 Jan Van Vessem Award and of the ISSCC 2013 Jack Kilby Award and the winner of the 2012 STM Technology Council Innovation Prize, for having introduced on the company’s roadmap the integrated CMOS THz technology for imaging applications. Andreia is ESSCIRC TPC Vice-Chair in Cracow 2019, and will be the TPC chair of ESSCIRC 2020 in Grenoble.
